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課程名稱 |
交換電路與邏輯設計
Switching Circuit and Logic Design |
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開課學期 |
110-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
江介宏 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
02 |
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學分 |
3.0 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四8(15:30~16:20)星期五8,9(15:30~17:20) |
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上課地點 |
明達231明達231 |
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備註 |
本系優先
總人數上限：80人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1101LD02 |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
「交換電路與邏輯設計」課程將介紹如何以「開關」(switch)作為實現布林邏輯與設計數位電路之基本元件，並介紹如何有系統地優化交換電路(switching circuit)。
課程內容包括：
Introduction
- Number Systems and Conversion
Boolean Algebra and its Applications
- Combinational Logic Design and its Minimization
- Karnaugh Maps and Two-Level Logic Minimization
- Multi-Level Gate Circuits
- Combinational Circuit Design
- Multiplexers, Decoders, and Programmable Logic Decices
Sequential Logic Design and its Minimization
- Latches and Flip-Flops
- Registers and Counters
- Analysis of Clock Sequential Circuits
- Derivation of State Graphs and Tables
- Reduction of State Tables
- Sequential Circuit Design
- Circuits for Arithmetic Operations
Hardware Description Language: Verilog (basics)
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課程目標 |
數位系統在我們的日常生活中無所不再，「交換電路與邏輯設計」課程將帶領同學們進入「零」與「壹」的世界，了解二元邏輯如何能勝任所有的計算工作。
本課程將提供其他進階課程﹝如「數位積體電路設計」、「電子設計自動化導論」、「計算機組織與架構」、「邏輯合成與驗證」、「積體電路測試」等課程﹞之入門知識。 |
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課程要求 |
無預修科目 |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
C. H. Roth Jr. Fundamentals of Logic Design, 7th Edition, Cengage Learning, 2013 |
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參考書目 |
待補 |
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評量方式
(僅供參考) |
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週次 |
日期 |
單元主題 |
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第1週 |
09/23, 24 |
§1 Introduction, Number Systems and Conversion; §2 Boolean Algebra |
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第2週 |
09/30, 10/01 |
§2 Boolean Algebra; §3 Boolean Algebra (Continued) |
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第3週 |
10/07, 08 |
§3 Boolean Algebra (Continued); §4 Applications of Boolean Algebra |
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第4週 |
10/14, 15 |
(10/14) Quiz 1 (§1 ~ §3); (10/15) §5 Karnaugh Maps |
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第5週 |
10/21, 22 |
§7 Multi-Level Gate Circuits; §8 Combinational Circuit Design (skip Fig. 8-12 and 8-14) |
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第6週 |
10/28, 29 |
(10/28) Quiz 2 (§4 ~ §5); (10/29) §8 Combinational Circuit Design; §9 Multiplexers, Decoders, and Programmable Logic Devices (skip §9.7) |
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第7週 |
11/04, 05 |
§9 Multiplexers, Decoders, and Programmable Logic Devices; §11 Latches and Flip-Flops |
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第8週 |
11/11, 12 |
(11/11) Review Session; (11/12) Midterm Exam (§1~§9) |
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第9週 |
11/18, 19 |
§11 Latches and Flip-Flops; §12 Registers and Counters |
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第10週 |
11/25, 26 |
(11/25) §12 Registers and Counters; (11/26) Combinational Circuit Design Using Altera Quartus II (held by TA) |
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第11週 |
12/02, 03 |
(12/02) §12 Registers and Counters; §13 Analysis of Clocked Sequential Circuits; (12/03) NTU Anniversary (no class) |
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第12週 |
12/09, 10 |
§13 Analysis of Clocked Sequential Circuits |
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第13週 |
12/16, 17 |
(12/16) Quiz 3 (§11 ~ §13); (12/17) §14 Derivation of State Graphs and Tables (skip Examples 2, 3 of §14.3) |
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第14週 |
12/23, 24 |
§14 Derivation of State Graphs and Tables (skip Examples 2, 3 of §14.3); §15 Reduction of State Table (§15.1 ~ §15.3); §16 Sequential Circuit Design (§16.1 ~ §16.4) |
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第15週 |
12/30, 31 |
(12/30) §16 Sequential Circuit Design; (12/31) New Year Weekend (no class) |
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第16週 |
01/06, 07 |
(01/06) Review Session; (01/0)7 Final Exam (§11~§16) |
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第17週 |
01/13, 14 |
(01/13) Supplementary Material (FPGA); (01/14) Sequential Circuit Design Using Altera Quartus II (held by TA) |
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第18週 |
01/20, 21 |
Supplementary Material (Advanced Topics: Logic and Computation, Computation with Biochemistry and Quantum Physics, EDA) |
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